The subject matter disclosed herein generally relates to a three level inverter midpoint and, more particularly, to controlling voltage at the DC midpoint of the three level inverter.
Three level inverters have a DC midpoint terminal in addition to a DC positive and a DC negative terminal. Because of the particular arrangement of the DC midpoint, the DC midpoint node voltage is not controlled by a power source. Therefore, the DC midpoint node voltage can move relative to ground. This imbalance is minimized in order to maintain output current power quality and limit insulated-gate bipolar transistor (IGBT) and DC capacitor voltage stress.
Therefore, one or more methods and system elements have been developed to control the DC midpoint voltage. For example, one method of controlling the DC midpoint voltage of a three-level inverter is to utilize a PI regulator. Specifically, the input to the PI regulator is the error in the DC midpoint voltage. A zero-sequence voltage, proportional to the PI regulator output, is applied on the inverter output to reduce the error in the DC midpoint voltage. This loop gain increases as the output power of the inverter increases. Consequently the system may grow unstable at different operating points.
Accordingly for at least the above discussed reasons, as well as others, there is a desire to provide improved control methods for a three level inverter DC midpoint voltage.